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Synopsys Jobs

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1 - 15 of 15
Search Results - Synopsys Jobs
apartmentSynopsys, Inc.placeDublin Pikeevent_available
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP...
placeCorklanguagecv-library.ieevent_available
in: RTL to Gate: Synopsys tools (scripting, synthesis, formality, ATPG, timing closure) Gate to GDS: Cadence tools (scripting, place & route, clock tree generation, GDS generation, timing closure, power/signal integrity, DRC, LVS, electromigration, antenna...
apartmentSynopsys, Inc.placeDublinlanguageappcast.ioevent_available
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP...
apartmentAdvanced Micro Devices IncplaceDublinevent_available
in semiconductor design verification. Strong proficiency in SystemVerilog and UVM methodology. Experience with verification tools such as VCS, Questa, and Synopsys tools. Experience with scripting languages such as Python, Perl, or TCL is a plus. Excellent problem...
apartmentTyndall National InstituteplaceCorklanguageappcast.ioevent_available
architectures for high-speed transceivers.  •  Hands-on experience with FPGA prototyping and ASIC development flows.  •  Familiarity with EDA tools (Cadence, Synopsys, Mentor Graphics) for digital design and verification.  •  Strong programming skills in MATLAB...
apartmentAdvanced Micro Devices IncplaceCorkevent_available
verbal, and presentation) and excellent time management. Proficiency with industry-standard EDA tools for Physical Design and Signoff flows, such as: Synopsys FusionCompiler, PrimeTime, StarRC Cadence Innovus Mentor Graphics Calibre Apache Redhawk...
apartmentQualcommplaceCorklanguageappcast.ioevent_available
restructuring, DFT logic implementation, Formal Verification.  •  Experience in handling MV designs and knowledge of lower checks like CLP.  •  Experience in Floor planning for 4nm and below technologies.  •  Place & Route tool experience on Synopsys ICC2/FC...
apartmentEuropean Tech RecruitplaceDublin Pikeevent_available
Keywords: ASIC / Physical Design / SoC / RTL / GDS / Place & Route / STA / RTL‑to‑GDS / IP Design / Digital Design / Cadence / Synopsys / Semiconductor / Timing Closure / PPA Optimization Location: Dublin, County Dublin, Ireland Employment type: Full‑time...
apartmentAdvanced Micro Devices IncplaceCorkevent_available
verbal, and presentation) and excellent time management. Proficiency with industry-standard EDA tools for Physical Design and Signoff flows, such as: Synopsys Fusion Compiler, Prime Time, Star RC Cadence Innovus Mentor Graphics Calibre Apache Redhawk...
apartmentQualcommplaceCorklanguageappcast.ioevent_available
requirement  •  Experienced in Floorplanning lower technologies 4nm and below  •  Place & Route tool experience on Synopsys FC and/or Cadence Innovus  •  Placement (experienced in mitigating legalization, secPG routing and congestion challenges), CTS (Skew balancing...
apartmentAdvanced Micro Devices IncplaceCorkevent_available
verbal, and presentation) and excellent time management. Proficiency with industry-standard EDA tools for Physical Design and Signoff flows, such as: Synopsys FusionCompiler, PrimeTime, StarRC Cadence Innovus Mentor Graphics Calibre Apache Redhawk...
apartmentInfineon Technologies AGplaceDublinlanguageappcast.ioevent_available
on microcontroller architectures and IP development  •  Understanding of digital design flows and tools, including front-end design and verification tools (e.g., Cadence, Synopsys, Mentor)  •  Proven leadership experience, managing teams of design engineers in a high...
apartmentSoftware PlacementsplaceCorklanguageappcast.ioevent_available
Verilog for coding and verification.  •  Proficiency in RTL design techniques, including synthesis, timing closure, and verification.  •  Experience in using UVM for functional verification of ASIC designs.  •  Experience with EDA tools like Cadence and Synopsys...
apartmentmicroTECH Global LimitedplaceDublinlanguageappcast.ioevent_available
Familiarity with PCB and substrate design.  •  Knowledge of industry standards such as IPC, JEDEC, and SEMI.  •  Proficiency in EDA tools like Cadence Allegro, Mentor Graphics, or Synopsys. #J-18808-Ljbffr...
apartmentmicroTECH Global LimitedplaceDublinlanguageappcast.ioevent_available
or more EM extraction/field solver tools (e.g., Cadence Clarity, Ansys HFSS/SIwave, CST Studio, Keysight ADS, Synopsys Raptor, or similar).  •  Experience with PCB parasitic extraction, EM modeling, and high-frequency simulation.  •  Solid background...
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